The field of this invention relates to an integrated circuit, a communication unit and a method for power detection. The invention is applicable to, but not limited to, an integrated circuit comprising a squaring circuit for a wireless communication unit.
In the field of wireless communication systems, power control is needed in a radio access network to allow the transceivers in a base station (referred to as a Node-B in a 3rd generation partnership project (3GPP™) communication standard within the universal mobile telecommunication system (UMTS™)) and the transceivers in a subscriber wireless communication unit (referred to as a user equipment (UE) in 3GPP™) to adjust their transmitter output power level to take into account the geographical distance between them. The closer that the subscriber wireless communication unit (UE) is to the base station's (e.g. Node B's) transceiver, the less power the UE and the Node B's transceivers are required to transmit, for the transmitted signal to be adequately received by the other communication unit. Such a transmit ‘power control’ feature saves battery power in the UE and also helps to reduce the level of potential interference within the communication system. Initial power settings for the UE, along with other control information, are typically set by the information provided on a beacon physical channel in each particular communication cell. Accurate control of the output power level of such wireless communication units is typically achieved by employing a feedback path from an output of the transmitter, to route a portion of the transmit signal to processing circuitry to allow the current power level of the transmit signal to be determined, and hence any gain/attenuation adjustment required.
Furthermore, a large number of conventional radio frequency (RF) transmitters use linear power amplifiers (PAs) to enable a wireless communication unit to transmit large amounts of data within a limited frequency bandwidth Accordingly, the power efficiency of such conventional RF transmitters is usually very low, due to the low efficiency of the linear PAs used therein. Hence, linearization techniques are also often employed with the linear PAs, as an attractive alternative to conventional linear PAs within RF transmitters. The vast majority of linearization techniques require the use of feedback signals from an output of the linear PA.
Thus, for reasons of both power control and/or linearization, feedback of the radio frequency signal to be transmitted is performed, so that appropriate signal processing of the initial baseband signal, and/or components or circuits in the transmit path, can be controlled. Hence, most present day wireless transmitters include a feedback path to route the transmit signal back to a digital processing block, in order to determine a power level or linearity of the signal being transmitted. This information is used to control, for example, the gain stages of the transmitter chain. Thus, in effect, the feedback path comprises a power detector circuit/architecture.
Often the power detector circuit comprises, in effect, a down-conversion receiver to convert and attenuate the transmit radio frequency signal to a baseband output that can be digitally processed to calculate the root mean square (RMS) value of the transmit signal. Typically, the RF down-conversion low-noise amplifier (LNA) and down-conversion mixers are designed for temperature stable gain, to ensure that there is no variation in the gain of the circuit across a wide temperature range. The input signal is typically fed from a power amplifier coupler, located between the PA output and, say a duplex switch.
In the feedback path, a conversion circuit to convert the RMS signal to a DC signal, often referred to as RMS-to-DC converters, can be used. RMS-to-DC converters are used to convert the RMS (root-mean-square) value of an arbitrary signal into a quasi-DC signal that represents the true power level of the signal. It is known that some RMS-to-DC converters, use an architecture of balanced squaring cells that are capable of measuring an approximation of the power at microwave frequencies, as illustrated in FIG. 1. High performance squaring circuits generally fall into either of the following two classifications: (i) Multiplier-Circuits configured to implement the square function; or (ii) circuits that directly utilise the trans-conductance Square-Law characteristic of a MOS transistor.
The architecture 100 of FIG. 1 proposes a temperature-stabilised RMS-to-DC converter that uses wide-band, matched squaring circuits. Here, RMS-to-DC conversion is achieved by applying an input signal 105 to be measured to a first squaring cell/circuit (denoted by ‘x2’) 110. A voltage is generated at the output of the squaring cell/circuit and is determined by the output current signal into the load resistor whose other end is connected to a supply voltage. The voltage at the output of the first squaring cell/circuit 110 has high frequency content, which is filtered by the filter capacitor to provide a ‘mean’ low frequency signal into the non-inverting input of the Error-Amplifier (denoted by ‘Error amp’). The feedback path 115 around the Error Amplifier, which includes the second squaring cell/circuit (denoted by ‘x2’) 120, forms an analogue tracking loop such that the voltage at the input of the Error-Amplifier (error-node) is nulled. As a result the signal at the output of the Error-Amplifier, which also forms the input to second squaring cell/circuit 120, represents the RMS value of the input signal 105. In this circuit, the RMS voltage is scaled by the buffer to increase the magnitude of the measured voltage for use on the power measurement system. By implementing the squaring cells/circuits 110, 120 as series-connected three-transistor multi-tan h transconductance cells, it is suggested in the literature that square law approximation from DC up to microwave frequencies can be achieved.
However, it is noted that the architecture of FIG. 1 suffers from sensitivity to DC offsets at the error amplifier input, which limits the functional dynamic range of the circuit. In order to minimize the sensitivity to DC offsets, added complexity is required to auto-zero the internal offsets. Furthermore, the architecture of FIG. 1 also suffers from output noise of the error amplifier, which is strongly dependent upon the gain in the feedback path. Since the feedback path contains a squaring function, the feedback path gain is proportional to the signal amplitude. Thus, the noise gain of the system increases for small signal levels, thereby again limiting the Dynamic Range. Notably, the analog filter included in this detector system is large and will occupy significant die area if the system is implemented on an integrated circuit.
The paper titled “An MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuits with Source Followers”, Ho-Jun Song and Choong-Ki Kim, IEEE JSSC, vol. 25, No. 3, June 1990” proposes the multiplication of two voltages, V1 & V2, based on the “difference” of the ‘square of the sum of the two voltages’ and the ‘square of the difference of the two voltages’, whereby:Vo=(V1+V2)2−(V1−V2)2=4·V1·V2  [1]
The squaring is achieved using the square-law relationship of the drain-current, ID, to gate-source voltage, VGS, of a MOS transistor operating in the saturation region. If inputs V1 & V2 are applied to the gate and source of a MOS transistor respectively, the drain current is proportional to the square of the difference of the voltages:
                              I          D                =                              K            2                    ·                      (                          W              L                        )                    ·                                    (                                                V                  GS                                -                                  V                  T                                            )                        2                                              [        2        ]            
Where, K=μ0·COX 
μ0 represents the carrier mobility,
COX the gate capacitance per unit area, and
VT is the threshold voltage of the MOS transistor.
The core squaring circuit 200 has two differential input voltages V1 (V1+ and V1−) & V2 (V2+ and V2−) and a single output current (Isq) as shown in FIG. 2.
In FIG. 2, transistors M1 & M2 act as source-follower stages and transfer the input voltage (V2) to the sources of M3 & M4 respectively. For the squaring function to be fully compliant the voltages across the source followers should be independent of the input gate signal voltage level. In practice the current in the source-followers changes with input voltage; as more current is forced to flow in the ‘squaring transistors’ (M3 & M4). In order that this effect is minimised there is the following requirement for the Width/Length ratios of the source follower transistors compared to the squaring transistors:
                                          (                          W              L                        )                                              M              ⁢                                                          ⁢              1                        ,                          M              ⁢                                                          ⁢              2                                      >>                                  ⁢                              (                          W              L                        )                                              M              ⁢                                                          ⁢              3                        ,                          M              ⁢                                                          ⁢              4                                                          [        3        ]            
and for this condition:
                              I          sq                ≈                              1            4                    ·          K          ·                                    (                              W                L                            )                                                      M                ⁢                                                                  ⁢                3                            ,                              M                ⁢                                                                  ⁢                4                                              ·                                    (                                                V                  1                                +                                  V                  2                                            )                        2                                              [        4        ]            
According to Equation [1] above, multiplication can be achieved by subtracting the ‘square of the difference’ from ‘the square of the sum’ of the two input voltages. Therefore if a second core squaring cell is configured to realise the ‘square of the difference’, and if V1=V2=Vin, it is possible to configure the squaring circuit to have both differential inputs and outputs (I1−I0), as shown in the core squaring circuit 300 of FIG. 3.
                              (                                    I              1                        -                          I              0                                )                ≈                              {                          K              ·                                                (                                      W                    L                                    )                                                                      M                    ⁢                                                                                  ⁢                    5                                    ,                  6                  ,                  7                  ,                  8                                                      }                    ·                      V            in            2                                              [        5        ]            
However, a primary assumption in the analysis of the above circuit is that the source-follower devices (M1-M4) provide a constant voltage drop over the range of input signal voltages. In practice the current in the source-followers varies, and therefore the gate-source voltage varies so as to provide current for the squaring devices (M5-M8). The authors acknowledge that “it is one of the significant error sources for this type of multiplier”. This ‘approximation-error’ acts in addition to other non-idealities associated with the MOS transistors, such as ‘velocity-saturation’, ‘mobility-degradation’, ‘short channel effects’ and ‘device mismatches’.
Thus, a need exists for an improved integrated circuit and method of operation that can preferably be applied to a wideband power detector (e.g. DC to several GHz) and can be implemented in a differential configuration that is insensitive to common-mode voltages at the input, and preferably has low supply voltage (headroom) requirements (≦1.35V operation).